Principal Design Enablement Engineer - Design Manual

About GlobalFoundries

GlobalFoundries is a world-leading contract manufacturer for the global semiconductor industry with facilities in Dresden, Singapore, New York and Vermont (USA). Our products are used in various technical applications, e.g. mobile communications, consumer electronics, automotive and more. GlobalFoundries employs around 13,000 people worldwide, including 280 in Sofia.
Our Sofia based team will enhance GF’s scale and capabilities, while strengthening competitiveness of its specialized application solutions to further position the company for growth and value creation.
Our Design and Technology Enablement teams are working on the development of a broad portfolio of semiconductor technologies ranging from 350 nm down to 12nm including FD-SOI, RF, High-Voltage and automotive applications.

Your Job

GlobalFoundries (GF) is seeking experienced, motivated engineers to take on the exciting challenge of design rule development for advanced CMOS FinFET and FD-SOI technologies.

This Principal Engineer (Level 6) position is within GF’s Ultra-low Power CMOS Product Line, Design Enablement / PDK / Design Manual Engineering Department, located in Sofia, Bulgaria.

As part of a dynamic team of semiconductor development and software engineering experts, the selected candidate will contribute to the development and enhancement of ultra-low power CMOS technology nodes for emerging applications in IoT, Mobile, Automotive, AI, and RF/5G, including advanced 12 nm FinFET, FD-SOI, and packaging technologies.

Responsibilities

The successful candidate will:

• Develop and define design rules for Front End of Line (FEOL), Middle of Line (MOL), Back End of Line (BEOL), and advanced packaging solutions

• Work closely with device and process integration engineers to align technology requirements, process assumptions, and design rules to ensure a unified technology definition

• Utilize simulation/calculation tools for variation analysis to determine optimal design rule values and margins, including worst-case scenarios

• Collaborate with designers, design enablement teams, and device/PCell engineers to develop special requests and produce high-quality design rule sets with full fail-mode analysis

• Define design rule validation priorities with GF’s fab integration team, ensuring business processes and procedures are met

• Contribute to the early stages of technology definition, establishing parametric goals aligned with GF’s roadmap and product offerings

• Act as a key interface between external customers, design enablement teams, and technology development groups, ensuring design rules, electrical constraints, and reliability are well-defined

• Continuously seek to improve methodologies through innovation

Required Qualifications

• Bachelor's or Master's degree in Electronics, Semiconductor Industry-related fields, Physics, or related disciplines

• Strong knowledge of chip design development workflows and verification flows

• Experience in design tools, physical layout design, and process/design interactions

• Excellent communication, interpersonal, and project management skills

• Understanding of design for manufacturing processes—programming experience is a plus

Preferred Qualifications

• Deep knowledge of semiconductor device physics and advanced process technology

• Experience with FinFET, FD-SOI, and advanced packaging technologies

• Prior exposure to customer interactions in design

• Strong grasp of process and design layout interactions, failure mode and effects analysis (FMEA), and mask-to-layout relationships

• Familiarity with advanced packaging workflows and verification flows

• Knowledge of COVENTOR, SPX 3D process simulation tools, Cadence, Calibre, and industry-standard EDA tools

• Experience with Python, SVRF, Tcl is highly desirable

We Offer

• Attractive compensation package with competitive salary, performance related bonus plan and a global recognition program.

• Employee Stock Purchase Plan (including 20% match and 50 seed shares for first time participants, non-executive).

• Individual, technical or management career path opportunities supported by enhanced learning and development programs.

• Healthy and teambuilding work environment with various perks:

  • Additional medical service, including dental and, coverage of employees’ children

  • Food vouchers and canteen discounts

  • Sports card 50% subsidized by the employer; possibility to add a family member.

  • Top-rated office location with recreation Spa facilities

  • Discounts for Spa & Wellness Programs at NV Tower

  • Regular Team Events and Celebrations

• Focus on employee work-life balance:

  • Hybrid working model and flexible working time

  • 21 to 25 days paid vacation depending on years with the company

GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard.