GlobalFoundries (GF) is one of the world’s leading semiconductor manufacturers. GF is redefining innovation and semiconductor manufacturing by developing and delivering feature-rich process technology solutions that provide leadership performance in pervasive high growth markets. GF offers a unique mix of design, development, and fabrication services. With a talented and diverse workforce and an at-scale manufacturing footprint spanning the U.S., Europe and Asia, GF is a trusted technology source to its worldwide customers. For more information, visit www.gf.com. GlobalFoundries is an Equal Employment Opportunity/Affirmative Action (EEO/AA) employer Minorities/Female/Disabled/Veteran (M/F/D/V).#CB

Bulgaria

Sofia

GlobalFoundries

About GlobalFoundriesGlobalFoundries is a world-leading contract manufacturer for the global semiconductor industry with facilities in Dresden, Singapore, New York and Vermont (USA). Our products are used in various technical applications, e.g. mobile communications, consumer electronics, automotive and more. GlobalFoundries employs around 13,000 people worldwide, including 280 in Sofia. Our Sofia based team will enhance GF’s scale and capabilities, while strengthening competitiveness of its specialized application solutions to further position the company for growth and value creation. Our Design and Technology Enablement teams are working on the development of a broad portfolio of semiconductor technologies ranging from 350 nm down to 12nm including FD-SOI, RF, High-Voltage and automotive applications.Your JobGlobalFoundries (GF) is seeking experienced, motivated engineers to take on the exciting challenge of design rule development for advanced CMOS FinFET and FD-SOI technologies.This Principal Engineer (Level 6) position is within GF’s Ultra-low Power CMOS Product Line, Design Enablement / PDK / Design Manual Engineering Department, located in Sofia, Bulgaria.As part of a dynamic team of semiconductor development and software engineering experts, the selected candidate will contribute to the development and enhancement of ultra-low power CMOS technology nodes for emerging applications in IoT, Mobile, Automotive, AI, and RF/5G, including advanced 12 nm FinFET, FD-SOI, and packaging technologies.ResponsibilitiesThe successful candidate will: <ul><li>Develop and define design rules for Front End of Line (FEOL), Middle of Line (MOL), Back End of Line (BEOL), and advanced packaging solutions</li><li>Work closely with device and process integration engineers to align technology requirements, process assumptions, and design rules to ensure a unified technology definition</li><li>Utilize simulation/calculation tools for variation analysis to determine optimal design rule values and margins, including worst-case scenarios</li><li>Collaborate with designers, design enablement teams, and device/PCell engineers to develop special requests and produce high-quality design rule sets with full fail-mode analysis</li><li>Define design rule validation priorities with GF’s fab integration team, ensuring business processes and procedures are met</li><li>Contribute to the early stages of technology definition, establishing parametric goals aligned with GF’s roadmap and product offerings</li><li>Act as a key interface between external customers, design enablement teams, and technology development groups, ensuring design rules, electrical constraints, and reliability are well-defined</li><li>Continuously seek to improve methodologies through innovation</li></ul>Required Qualifications<ul><li>Bachelor's or Master's degree in Electronics, Semiconductor Industry-related fields, Physics, or related disciplines</li><li>Strong knowledge of chip design development workflows and verification flows</li><li>Experience in design tools, physical layout design, and process/design interactions</li><li>Excellent communication, interpersonal, and project management skills</li><li>Understanding of design for manufacturing processes—programming experience is a plus</li></ul>Preferred Qualifications<ul><li>Deep knowledge of semiconductor device physics and advanced process technology</li><li>Experience with FinFET, FD-SOI, and advanced packaging technologies</li><li>Prior exposure to customer interactions in design</li><li>Strong grasp of process and design layout interactions, failure mode and effects analysis (FMEA), and mask-to-layout relationships</li><li>Familiarity with advanced packaging workflows and verification flows</li><li>Knowledge of COVENTOR, SPX 3D process simulation tools, Cadence, Calibre, and industry-standard EDA tools</li><li>Experience with Python, SVRF, Tcl is highly desirable</li></ul>We Offer<ul><li>Attractive compensation package with competitive salary, performance related bonus plan and a global recognition program.</li><li>Employee Stock Purchase Plan (including 20% match and 50 seed shares for first time participants, non-executive).</li><li>Individual, technical or management career path opportunities supported by enhanced learning and development programs.</li><li>Healthy and teambuilding work environment with various perks:<ul><li>Additional medical service, including dental and, coverage of employees’ children</li><li>Food vouchers and canteen discounts</li><li>Sports card 50% subsidized by the employer; possibility to add a family member.</li><li>Top-rated office location with recreation Spa facilities</li><li>Discounts for Spa &amp; Wellness Programs at NV Tower</li><li>Regular Team Events and Celebrations</li></ul></li><li>Focus on employee work-life balance:<ul><li>Hybrid working model and flexible working time</li><li>21 to 25 days paid vacation depending on years with the company</li></ul></li></ul>GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard.<div><div>Information about our benefits you can find here: <a href="https://gf.com/careers/opportunities-in-europe/" target="_blank" rel="noopener noreferrer">https://gf.com/careers/opportunities-in-europe/</a></div></div>

Full Time

Regular employment

Engineers and Technical Occupations

Principal Design Enablement Engineer - Design Manual

English

3D Modeling

Artificial Intelligence

Automotive

Design Patterns

Integration

Interaction Design

Layout

Manufacturing

Mobile Application Development

Project Management

Python

Statistical Analysis

Technology

Wireless Technologies

IoT knowledge  - a strong advantage

Jenkins

business process modeling

Workflow Management

ETL tools

Fintech

physics

Packaging

Secure Design

FMEA

Hybrid

<div><div>About GlobalFoundries&nbsp;</div><div>GlobalFoundries is a world-leading contract manufacturer for the global semiconductor industry with facilities in Dresden, Singapore, New York and Vermont (USA). Our products are used in various technical applications, e.g. mobile communications, consumer electronics, automotive and more. GlobalFoundries employs around 13,000 people worldwide, including 280 in Sofia.&nbsp;</div><div>Our Sofia based team will enhance GF’s scale and capabilities, while strengthening competitiveness of its specialized application solutions to further position the company for growth and value creation.&nbsp;</div><div>Our Design and Technology Enablement teams are working on the development of a broad portfolio of semiconductor technologies ranging from 350 nm down to 12nm including FD-SOI, RF, High-Voltage, and automotive applications.&nbsp;</div><div>&nbsp;</div><div>Your Job</div></div>Design, develop, and utilize testsites which are in-house chip designs used to develop and understand the technology of interest.&nbsp;<ul><li>Design Lead for testsite content focused on advanced packaging technologies. Drive inputs from stakeholders and creates solutions for electrically testable structures that will be created through silicon processes. Use EDA tools for automated layout generation and verification that proper layout was created.</li><li>Testsite coordinator role to drive tapeout readiness setup. Interact with various organizations involved in the tapeout setup and execution, set schedules and ensure technical needs are answered by responsible groups across the organization so that the final testsite is delivered with all requirements met.</li><li>Use the Skill language to write pCells and wiring scripts used in the design process</li><li>Be able to understand and interpret DRC results on designs and collaborate with stakeholders to successfully resolve DRC issues</li><li>Be able to work collaboratively across time zones to support the needs of stakeholders across the globe </li><li>Be able to execute and debug internal automation which is used to create designs</li><li>Be familiar with Cadence Virtuoso and Mentor Graphics Calibre tools</li><li>Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety &amp; Security requirements and programs </li><li>Work and collaborate on other projects and/or assignments as needed</li></ul>&nbsp; Required Qualifications&nbsp;<ul><li>Bachelor's or Master's degree in Electronics, Semiconductor Industry-related fields, Physics, or related disciplines</li><li>Strong knowledge of chip design development workflows and verification flows</li><li>Experience in design tools, physical layout design, and process/design interactions</li><li>Excellent communication, interpersonal, and project management skills</li><li>Understanding of design for manufacturing processes—programming experience is a plus</li></ul>We Offer&nbsp;<ul><li>Attractive compensation package with competitive salary, performance related bonus plan and a global recognition program.&nbsp;</li><li>Employee Stock Purchase Plan (including 20% match and 50 seed shares for first time participants, non-executive).&nbsp;</li><li>Individual, technical or management career path opportunities supported by enhanced learning and development programs.&nbsp;</li><li>Healthy and teambuilding work environment with various perks:&nbsp;<ul><li>Additional medical service, including dental and, coverage of employees’ children&nbsp;</li><li>Food vouchers and canteen discounts&nbsp;</li><li>Sports card 50% subsidized by the employer; possibility to add a family member.&nbsp;</li><li>Top-rated office location with recreation Spa facilities&nbsp;</li><li>Discounts for Spa &amp; Wellness Programs at NV Tower&nbsp;</li><li>Regular Team Events and Celebrations&nbsp;</li><li>Relocation/Immigration Support for international Hires&nbsp;</li></ul></li><li>Focus on employee work-life balance:&nbsp;<ul><li>Hybrid working model and flexible working time&nbsp;</li><li>21 to 25 days paid vacation depending on years with the company&nbsp;</li></ul></li></ul>We are constantly looking for specialists to strengthen our teams and would therefore be very pleased to receive your application. Upon receipt of your application, we will check the vacancies existing at this time and get back to you to coordinate the next steps.&nbsp;<div></div><div><div>Information about our benefits you can find here: <a href="https://gf.com/careers/opportunities-in-europe/" target="_blank" rel="noopener noreferrer">https://gf.com/careers/opportunities-in-europe/</a></div></div>

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